1. Field of the Invention
The present invention relates to a reticle and a method of fabricating a semiconductor device suitable for verification of process accuracy and so forth.
2. Description of the Related Art
Any pattern transferred to a resist film using a reticle has been subjected to dimensional measurement for the purpose of confirming the accuracy. The measurement is made on a critical-dimension pattern dedicated for the measurement, previously transferred to the resist film, rather than on patterns configuring circuits for the practical use. It has been becoming more often to form the critical-dimension pattern on the dicing line.
FIG. 8 shows a schematic drawing of a conventional reticle. A reticle 101 is partitioned into a circuit area 102 having patterns configuring circuits for actual use formed therein, and a dicing area 103 provided therearound. The dicing area 103 has a critical-dimension pattern 104, but no circuit patterns, formed therein. The critical-dimension pattern 104 is formed in the center portion of the dicing area 103.
Twice or more number of times of transfer of the pattern onto the resist film formed on a wafer through such reticle 101, and successive development result in formation of dicing lines 112 extending longitudinally and transversely, and chip areas 111 surrounded by the dicing lines 112, as shown in FIG. 9. On the center line of the dicing lines 112, there are formed critical-dimension patterns 113 having a symmetric geometry. The area surrounded by a two-dot chain line in FIG. 9 corresponds to an area transferred by a single shot of light exposure. Two critical-dimension patterns 113 may seem to reside in this area, but it is to be noted that the critical-dimension pattern 113 on the right hand side is one transferred by another shot of light exposure.
When the resist film after the transfer and development is subjected to the dimensional measurement under a CD-SEM (critical dimension scanning electron microscope), one measurement-target chip area 111a out of a plurality of chip areas 111 is specified as shown in FIG. 10, and the position of the critical-dimension pattern 113 which resides on the left is specified. Distance between two linear portions configuring the critical-dimension pattern 113 is then measured. It is necessary herein in the measurement to measure the distance at a measurement point 114a on the measurement-target chip area 111a side, as viewed from the center line of the dicing line 112. This is because the measurement otherwise made at a measurement point 114b on the adjacent chip area 111b, which resides on the opposite side of the measurement-target chip area 111a on the basis of the critical-dimension pattern 113, may raise a confusion such that the CD-SEM displays a state of the dimensional measurement as if it is made on the adjacent chip area 111b, despite the actual measurement being made appropriately.
It is, however, difficult for the conventional method to discriminate the measurement point 114a on the measurement-target chip area 111a side as viewed from the dicing line 112, from the measurement point 114b on the adjacent chip area 111b side, so that the measurement may be made on the distance at the measurement point 114b by mistake.
Similar problems occur not only for the case where one chip is exposed by a single shot of light exposure, but also for the case where a plurality of chips are exposed by a single shot of light exposure.
Related arts are disclosed in Japanese Patent Application Laid-open No. Hei 8-148490, Japanese Patent Application Laid-open No. Hei 5-333526, and Japanese Patent Application Laid-open No. Sho 59-55029.